Cypress Semiconductor /psoc63 /SRSS /PWR_TRIM_REF_CTL

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Interpret as PWR_TRIM_REF_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ACT_REF_TCTRIM 0ACT_REF_ITRIM 0ACT_REF_ABSTRIM 0 (ACT_REF_IBOOST)ACT_REF_IBOOST 0DPSLP_REF_TCTRIM 0DPSLP_REF_ABSTRIM 0DPSLP_REF_ITRIM

Description

Reference Trim Register

Fields

ACT_REF_TCTRIM

Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range

ACT_REF_ITRIM

Active-Reference current trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range

ACT_REF_ABSTRIM

Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range

ACT_REF_IBOOST

Active-Reference current boost. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: normal operation others: risk mitigation

DPSLP_REF_TCTRIM

DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range

DPSLP_REF_ABSTRIM

DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.

DPSLP_REF_ITRIM

DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.

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